# Approximate Wallace Tree Multiplier

Hearing aids must denoise and recognize speech within tight space and battery limits, and high-order finite impulse response filters cost area and power through many multiply-accumulate operations. This architecture places a memory-less, multiplier-less distributed-arithmetic FIR filter and a deep spectro neural network in one application-specific integrated circuit design, with inference using an approximate Wallace tree multiplier. Post-synthesis analysis reports 160,000 square micrometres, 1.4 milliwatts and about 2.1 milliseconds of hardware processing latency, while functional validation stays in MATLAB and prototype fabrication and real-time hardware validation remain future work.

Hearing aids must denoise and recognize speech within tight space and battery limits, and high-order finite impulse response filters cost area and power through many multiply-accumulate operations. This architecture places a memory-less, multiplier-less distributed-arithmetic FIR filter and a deep spectro neural network in one application-specific integrated circuit design, with inference using an approximate Wallace tree multiplier. Post-synthesis analysis reports 160,000 square micrometres, 1.4 milliwatts and about 2.1 milliseconds of hardware processing latency, while functional validation stays in MATLAB and prototype fabrication and real-time hardware validation remain future work.