A hearing-aid chip folds filtering and recognition into one ASIC: 160,000 square micrometres and 1.4 milliwatts after synthesis
Synopsis
Hearing aids must denoise and recognize speech within tight space and battery limits, and high-order finite impulse response filters cost area and power through many multiply-accumulate operations. This architecture places a memory-less, multiplier-less distributed-arithmetic FIR filter and a deep spectro neural network in one application-specific integrated circuit design, with inference using an approximate Wallace tree multiplier. Post-synthesis analysis reports 160,000 square micrometres, 1.4 milliwatts and about 2.1 milliseconds of hardware processing latency, while functional validation stays in MATLAB and prototype fabrication and real-time hardware validation remain future work.
Interpretation
Speech enhancement and speech recognition for a hearing aid are merged into one application-specific integrated circuit architecture rather than split into a filter front end and a separate neural-network inference block. Finite impulse response filters perform well in hearing aids, but high-order filters need many multiplication and addition operations, which raises hardware area and power consumption. Post-synthesis application-specific integrated circuit analysis reports an implementation area of 160,000 square micrometres and power consumption of 1.4 milliwatts, with functional validation carried out in MATLAB.
The filtering stage performs its multiply-accumulate work without general multipliers, using table-lookup accumulation instead. That path is a memory-less, multiplier-less distributed-arithmetic finite impulse response filter, which turns multiplication into look-up accumulation over input-bit combinations. On the recognition side, the deep spectro neural network uses an approximate Wallace tree multiplier built from approximate compressor adders during inference, and the whole design is evaluated through an application-specific integrated circuit post-synthesis flow.
Speed and latency figures are reported alongside area and power to place the architecture on a hearing-aid time scale. Post-synthesis results give a maximum throughput of 121.1 MHz, corresponding to a system critical-path delay of approximately 8.26 ns. After speech-frame acquisition, hardware processing latency is approximately 2.1 ms, with an area-delay product of 1,321,222 square micrometres times nanoseconds and a power-delay product of 11.56 milliwatts times nanoseconds.
Perspective
The evaluation is limited to MATLAB functional validation and application-specific integrated circuit post-synthesis analysis for hearing-aid speech processing; prototype fabrication and real-time hardware validation are named as future work.
The reported area, power, throughput and latency are post-synthesis analysis results and have not been measured on a fabricated chip or in real time; the conclusion gives no specific numbers for speech-processing performance metrics.