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# Speech Enhancement

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  1. A hearing-aid chip folds filtering and recognition into one ASIC: 160,000 square micrometres and 1.4 milliwatts after synthesis

    Hearing aids must denoise and recognize speech within tight space and battery limits, and high-order finite impulse response filters cost area and power through many multiply-accumulate operations. This architecture places a memory-less, multiplier-less distributed-arithmetic FIR filter and a deep spectro neural network in one application-specific integrated circuit design, with inference using an approximate Wallace tree multiplier. Post-synthesis analysis reports 160,000 square micrometres, 1.4 milliwatts and about 2.1 milliseconds of hardware processing latency, while functional validation stays in MATLAB and prototype fabrication and real-time hardware validation remain future work.

  2. arXiv

    Smart glasses two-person transcription gets a frontend: separating speakers before the audio-language model cuts errors on overlapped speech

    For time-stamped speaker-attributed transcription of two-person smart-glasses conversations, extracting or separating each target speaker before decoding lowers error rates, and the gain grows with the speech overlap ratio on the validation set.

  3. arXiv

    Does per-frame early exit pay off? A dynamic-depth speech enhancer lands on the same latency-quality frontier as static models on STM32N6, with a 26 microsecond per-frame policy

    The work supervises every intermediate depth of one causal speech enhancement model and fine-tunes its output heads so deeper outputs are never worse than shallower ones, yielding a family of static models that are more Pareto-efficient than equivalently-sized counterparts trained from scratch on the same budget (up to 0.11 higher PESQ at equivalent compute, matching the best PESQ at 30% less compute); after int8 quantization on an STM32N6 microcontroller, the dynamic enhancer lies on the same latency-quality frontier as the static models, with the policy running in 26 microseconds per frame on the companion Cortex-M55 and splitting the enhancer into separate NPU graphs adding 2.2% latency overhead.

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