# NVIDIA DSX MaxLPS

NVIDIA describes the deterministic execution model of the Groq 3 LPX low-latency accelerator within its Vera Rubin platform: the LPU compiler schedules compute and data movement down to the clock cycle, letting it predict per-cycle current demand and use Preemptive Power (PEP) and Clock Period Synthesis (CPS) to reduce voltage droop and shrink the voltage guardband, with internal testing showing over 60% less voltage drop, an estimated high single-digit percentage decrease in the baseline voltage that must be continually supplied, a potentially low-double-digit percentage reduction in power for the same workload, and up to 35x higher throughput per megawatt at the platform level versus the previous-generation GB200 NVL72 for 2T+ parameter models at long context and high interactivity.

NVIDIA describes the deterministic execution model of the Groq 3 LPX low-latency accelerator within its Vera Rubin platform: the LPU compiler schedules compute and data movement down to the clock cycle, letting it predict per-cycle current demand and use Preemptive Power (PEP) and Clock Period Synthesis (CPS) to reduce voltage droop and shrink the voltage guardband, with internal testing showing over 60% less voltage drop, an estimated high single-digit percentage decrease in the baseline voltage that must be continually supplied, a potentially low-double-digit percentage reduction in power for the same workload, and up to 35x higher throughput per megawatt at the platform level versus the previous-generation GB200 NVL72 for 2T+ parameter models at long context and high interactivity.

NVIDIA and Nscale jointly evaluated DSX MaxLPS policy-governed dynamic power allocation with Kimi K2.5 (FP4) inference workloads on NVIDIA GB300 NVL72 systems at Nscale's data center at the Verne campus in Keflavík, Iceland: under the same 264.4 kW approved power budget, managed GPUs rose from 140 to 192 (+37.1%), aggregate throughput rose from 1,084,503 to 1,618,443 tokens/s (+49.2%), throughput per provisioned watt rose from 4.10 to 6.12 tokens/s/W (+49.2%), median and P75 latency stayed within 5% of baseline, while P99 time to first token increased 17% from the 15.7-second baseline.

NVIDIA and Nscale jointly evaluated DSX MaxLPS policy-governed dynamic power allocation with Kimi K2.5 (FP4) inference workloads on NVIDIA GB300 NVL72 systems at Nscale's data center at the Verne campus in Keflavík, Iceland: under the same 264.4 kW approved power budget, managed GPUs rose from 140 to 192 (+37.1%), aggregate throughput rose from 1,084,503 to 1,618,443 tokens/s (+49.2%), throughput per provisioned watt rose from 4.10 to 6.12 tokens/s/W (+49.2%), median and P75 latency stayed within 5% of baseline, while P99 time to first token increased 17% from the 15.7-second baseline.