# NVIDIA Groq 3 LPX

NVIDIA describes the deterministic execution model of the Groq 3 LPX low-latency accelerator within its Vera Rubin platform: the LPU compiler schedules compute and data movement down to the clock cycle, letting it predict per-cycle current demand and use Preemptive Power (PEP) and Clock Period Synthesis (CPS) to reduce voltage droop and shrink the voltage guardband, with internal testing showing over 60% less voltage drop, an estimated high single-digit percentage decrease in the baseline voltage that must be continually supplied, a potentially low-double-digit percentage reduction in power for the same workload, and up to 35x higher throughput per megawatt at the platform level versus the previous-generation GB200 NVL72 for 2T+ parameter models at long context and high interactivity.

NVIDIA describes the deterministic execution model of the Groq 3 LPX low-latency accelerator within its Vera Rubin platform: the LPU compiler schedules compute and data movement down to the clock cycle, letting it predict per-cycle current demand and use Preemptive Power (PEP) and Clock Period Synthesis (CPS) to reduce voltage droop and shrink the voltage guardband, with internal testing showing over 60% less voltage drop, an estimated high single-digit percentage decrease in the baseline voltage that must be continually supplied, a potentially low-double-digit percentage reduction in power for the same workload, and up to 35x higher throughput per megawatt at the platform level versus the previous-generation GB200 NVL72 for 2T+ parameter models at long context and high interactivity.