Engineering Sciences

148 items

arXiv Sep 17, 2026
This work studies two salient behaviors of large language model (LLM) training loads—abrupt ramps at job initiation and termination that induce transient frequency excursions, and sustained periodic oscillations during training that produce oscillatory steady-state behavior—and proposes a grid-aware dynamic specification framework: for ramping loads it shows that nodal rotor frequencies can be accurately approximated by the center-of-inertia (COI) frequency and derives analytical expressions for its nadir and rate of change of frequency (RoCoF), which determine allowable combinations of ramp times and steady-state load demands satisfying prescribed frequency limits; for oscillatory loads it derives spectral specifications on their Fourier coefficients, shows the admissible coefficient set
This work studies two salient behaviors of large language model (LLM) training loads—abrupt ramps at job initiation and termination that induce transient frequency excursions, and sustained periodic oscillations during training that produce oscillatory steady-state behavior—and proposes a grid-aware dynamic specification framework: for ramping loads it shows that nodal rotor frequencies can be accurately approximated by the center-of-inertia (COI) frequency and derives analytical expressions for its nadir and rate of change of frequency (RoCoF), which determine allowable combinations of ramp times and steady-state load demands satisfying prescribed frequency limits; for oscillatory loads it derives spectral specifications on their Fourier coefficients, shows the admissible coefficient set
Designing Grid-Aware Dynamic Specifications for Large Data Center Loads
This work studies two salient behaviors of large language model (LLM) training loads—abrupt ramps at job initiation and termination that induce transient frequency excursions, and sustained periodic oscillations during training that produce oscillatory steady-state behavior—and proposes a grid-aware dynamic specification framework: for ramping loads it shows that nodal rotor frequencies can be accurately approximated by the center-of-inertia (COI) frequency and derives analytical expressions for its nadir and rate of change of frequency (RoCoF), which determine allowable combinations of ramp times and steady-state load demands satisfying prescribed frequency limits; for oscillatory loads it derives spectral specifications on their Fourier coefficients, shows the admissible coefficient set
This work studies two salient behaviors of large language model (LLM) training loads—abrupt ramps at job initiation and termination that induce transient frequency excursions, and sustained periodic oscillations during training that produce oscillatory steady-state behavior—and proposes a grid-aware dynamic specification framework: for ramping loads it shows that nodal rotor frequencies can be accurately approximated by the center-of-inertia (COI) frequency and derives analytical expressions for its nadir and rate of change of frequency (RoCoF), which determine allowable combinations of ramp times and steady-state load demands satisfying prescribed frequency limits; for oscillatory loads it derives spectral specifications on their Fourier coefficients, shows the admissible coefficient set
arXiv Sep 16, 2026
This work demonstrates on a live O-RAN testbed that two autonomous agents with individually correct objectives—one protecting a latency SLA and one maximizing utilization for energy efficiency—jointly drive recurring opposing excursions of the shared resource partition, and presents and proves a lightweight arbitration layer, AURA, whose three admission checks (feasibility invariants, per-variable dwell time, deadband) reduce shared-state excursion amplitude from 8.4 to 0.4 PRB and cross-slice throughput starvation from 40–55% to 0.3%, while leaving the protected slice's own latency compliance unchanged.
This work demonstrates on a live O-RAN testbed that two autonomous agents with individually correct objectives—one protecting a latency SLA and one maximizing utilization for energy efficiency—jointly drive recurring opposing excursions of the shared resource partition, and presents and proves a lightweight arbitration layer, AURA, whose three admission checks (feasibility invariants, per-variable dwell time, deadband) reduce shared-state excursion amplitude from 8.4 to 0.4 PRB and cross-slice throughput starvation from 40–55% to 0.3%, while leaving the protected slice's own latency compliance unchanged.
Taming the Agentic RAN: Stability-Guaranteed Arbitration of Autonomous AI Agents in O-RAN
This work demonstrates on a live O-RAN testbed that two autonomous agents with individually correct objectives—one protecting a latency SLA and one maximizing utilization for energy efficiency—jointly drive recurring opposing excursions of the shared resource partition, and presents and proves a lightweight arbitration layer, AURA, whose three admission checks (feasibility invariants, per-variable dwell time, deadband) reduce shared-state excursion amplitude from 8.4 to 0.4 PRB and cross-slice throughput starvation from 40–55% to 0.3%, while leaving the protected slice's own latency compliance unchanged.
This work demonstrates on a live O-RAN testbed that two autonomous agents with individually correct objectives—one protecting a latency SLA and one maximizing utilization for energy efficiency—jointly drive recurring opposing excursions of the shared resource partition, and presents and proves a lightweight arbitration layer, AURA, whose three admission checks (feasibility invariants, per-variable dwell time, deadband) reduce shared-state excursion amplitude from 8.4 to 0.4 PRB and cross-slice throughput starvation from 40–55% to 0.3%, while leaving the protected slice's own latency compliance unchanged.
MIT Technology Review Sep 16, 2026
This MIT Technology Review Insights conversation produced in partnership with Syensqo records the views of Mike Finelli, Syensqo's chief technology and innovation officer and chief North America officer: AI is pushing semiconductors and data centers toward physical limits, which piles up more simultaneous requirements on advanced materials, and Syensqo is responding by developing materials for high-voltage data center architectures, advanced sealing materials for semiconductor manufacturing, and thermal-management solutions including direct immersion cooling fluids, while working with Microsoft on AI agents that digitally synthesize millions of candidate molecules, predict their performance through physics-based simulation, and rank them down to roughly a hundred candidates for laboratory
This MIT Technology Review Insights conversation produced in partnership with Syensqo records the views of Mike Finelli, Syensqo's chief technology and innovation officer and chief North America officer: AI is pushing semiconductors and data centers toward physical limits, which piles up more simultaneous requirements on advanced materials, and Syensqo is responding by developing materials for high-voltage data center architectures, advanced sealing materials for semiconductor manufacturing, and thermal-management solutions including direct immersion cooling fluids, while working with Microsoft on AI agents that digitally synthesize millions of candidate molecules, predict their performance through physics-based simulation, and rank them down to roughly a hundred candidates for laboratory
Building the materials foundation for AI: Syensqo on advanced materials and AI as a two-way driver
This MIT Technology Review Insights conversation produced in partnership with Syensqo records the views of Mike Finelli, Syensqo's chief technology and innovation officer and chief North America officer: AI is pushing semiconductors and data centers toward physical limits, which piles up more simultaneous requirements on advanced materials, and Syensqo is responding by developing materials for high-voltage data center architectures, advanced sealing materials for semiconductor manufacturing, and thermal-management solutions including direct immersion cooling fluids, while working with Microsoft on AI agents that digitally synthesize millions of candidate molecules, predict their performance through physics-based simulation, and rank them down to roughly a hundred candidates for laboratory
This MIT Technology Review Insights conversation produced in partnership with Syensqo records the views of Mike Finelli, Syensqo's chief technology and innovation officer and chief North America officer: AI is pushing semiconductors and data centers toward physical limits, which piles up more simultaneous requirements on advanced materials, and Syensqo is responding by developing materials for high-voltage data center architectures, advanced sealing materials for semiconductor manufacturing, and thermal-management solutions including direct immersion cooling fluids, while working with Microsoft on AI agents that digitally synthesize millions of candidate molecules, predict their performance through physics-based simulation, and rank them down to roughly a hundred candidates for laboratory
Chemical Society reviews Sep 16, 2026
This review addresses active lithium loss during the initial cycling and long-term operation of lithium-ion batteries by establishing a classification framework for cathode lithium-rich compensators (LRCs) based on lithium compensation mechanisms, covering binary, ternary, over-lithiated, sacrificial lithium salt, and sustained-release types; it systematically summarizes their working principles, typical charge compensation pathways, and practical performance, discusses key challenges including air instability, gas evolution, high delithiation voltage, and processing issues, highlights mitigation strategies involving nanoscale engineering, surface coating, defect and doping design, and electrolyte optimization, and further proposes a synergistic multimodal lithium-compensation strategy int
This review addresses active lithium loss during the initial cycling and long-term operation of lithium-ion batteries by establishing a classification framework for cathode lithium-rich compensators (LRCs) based on lithium compensation mechanisms, covering binary, ternary, over-lithiated, sacrificial lithium salt, and sustained-release types; it systematically summarizes their working principles, typical charge compensation pathways, and practical performance, discusses key challenges including air instability, gas evolution, high delithiation voltage, and processing issues, highlights mitigation strategies involving nanoscale engineering, surface coating, defect and doping design, and electrolyte optimization, and further proposes a synergistic multimodal lithium-compensation strategy int
Cathode lithium-rich compensators for next-generation lithium-ion batteries: classification framework, challenges, and synergistic prelithiation strategies
This review addresses active lithium loss during the initial cycling and long-term operation of lithium-ion batteries by establishing a classification framework for cathode lithium-rich compensators (LRCs) based on lithium compensation mechanisms, covering binary, ternary, over-lithiated, sacrificial lithium salt, and sustained-release types; it systematically summarizes their working principles, typical charge compensation pathways, and practical performance, discusses key challenges including air instability, gas evolution, high delithiation voltage, and processing issues, highlights mitigation strategies involving nanoscale engineering, surface coating, defect and doping design, and electrolyte optimization, and further proposes a synergistic multimodal lithium-compensation strategy int
This review addresses active lithium loss during the initial cycling and long-term operation of lithium-ion batteries by establishing a classification framework for cathode lithium-rich compensators (LRCs) based on lithium compensation mechanisms, covering binary, ternary, over-lithiated, sacrificial lithium salt, and sustained-release types; it systematically summarizes their working principles, typical charge compensation pathways, and practical performance, discusses key challenges including air instability, gas evolution, high delithiation voltage, and processing issues, highlights mitigation strategies involving nanoscale engineering, surface coating, defect and doping design, and electrolyte optimization, and further proposes a synergistic multimodal lithium-compensation strategy int
Journal of Nondestructive Evaluation Sep 16, 2026
This study conditioned concrete prisms of four compressive strengths (f′c = 32–56 MPa) and two alkali-silica reaction (ASR) damaged specimens by compressive loading, monitored the subsequent velocity recovery with coda wave interferometry (CWI), and applied a self-referencing temperature correction to remove drift from ambient fluctuations of about ±0.2°C; for intact specimens the recovery rate mv and velocity drop magnitude |c| increased with strength (|c| from 3.08×10⁻⁴ to 6.02×10⁻⁴, mv from 6.77×10⁻⁵/s to 13.76×10⁻⁵/s) and recovery time shortened from 9.9 h to 6.
This study conditioned concrete prisms of four compressive strengths (f′c = 32–56 MPa) and two alkali-silica reaction (ASR) damaged specimens by compressive loading, monitored the subsequent velocity recovery with coda wave interferometry (CWI), and applied a self-referencing temperature correction to remove drift from ambient fluctuations of about ±0.2°C; for intact specimens the recovery rate mv and velocity drop magnitude |c| increased with strength (|c| from 3.08×10⁻⁴ to 6.02×10⁻⁴, mv from 6.77×10⁻⁵/s to 13.76×10⁻⁵/s) and recovery time shortened from 9.9 h to 6.
Slow Dynamics in Concrete: Effects of Temperature, Strength Variation, and Microcracking Damage
This study conditioned concrete prisms of four compressive strengths (f′c = 32–56 MPa) and two alkali-silica reaction (ASR) damaged specimens by compressive loading, monitored the subsequent velocity recovery with coda wave interferometry (CWI), and applied a self-referencing temperature correction to remove drift from ambient fluctuations of about ±0.2°C; for intact specimens the recovery rate mv and velocity drop magnitude |c| increased with strength (|c| from 3.08×10⁻⁴ to 6.02×10⁻⁴, mv from 6.77×10⁻⁵/s to 13.76×10⁻⁵/s) and recovery time shortened from 9.9 h to 6.
This study conditioned concrete prisms of four compressive strengths (f′c = 32–56 MPa) and two alkali-silica reaction (ASR) damaged specimens by compressive loading, monitored the subsequent velocity recovery with coda wave interferometry (CWI), and applied a self-referencing temperature correction to remove drift from ambient fluctuations of about ±0.2°C; for intact specimens the recovery rate mv and velocity drop magnitude |c| increased with strength (|c| from 3.08×10⁻⁴ to 6.02×10⁻⁴, mv from 6.77×10⁻⁵/s to 13.76×10⁻⁵/s) and recovery time shortened from 9.9 h to 6.
Science advances Sep 16, 2026
This work fabricates a chip-scale microwave diffractive neural network (MDNN) in a GaAs semiconductor process, integrating cascaded couplers and phase shifters to implement a diffraction network within a millimeter-scale footprint, reducing the size of conventional MDNNs by over four orders of magnitude, achieving a computational latency of 2.05 ns and a system-level energy efficiency of 0.83 TOPS/W, and reaching more than 86% accuracy across three functional prototypes—MNIST handwritten digit recognition, multi-user interference suppression, and real-time obstacle perception for drones—thereby validating the chip's capability to directly perform both digital image processing and in-situ electromagnetic information processing in the microwave domain.
This work fabricates a chip-scale microwave diffractive neural network (MDNN) in a GaAs semiconductor process, integrating cascaded couplers and phase shifters to implement a diffraction network within a millimeter-scale footprint, reducing the size of conventional MDNNs by over four orders of magnitude, achieving a computational latency of 2.05 ns and a system-level energy efficiency of 0.83 TOPS/W, and reaching more than 86% accuracy across three functional prototypes—MNIST handwritten digit recognition, multi-user interference suppression, and real-time obstacle perception for drones—thereby validating the chip's capability to directly perform both digital image processing and in-situ electromagnetic information processing in the microwave domain.
Microwave diffractive neural network chips: sensing and computing on a millimeter-scale GaAs chip
This work fabricates a chip-scale microwave diffractive neural network (MDNN) in a GaAs semiconductor process, integrating cascaded couplers and phase shifters to implement a diffraction network within a millimeter-scale footprint, reducing the size of conventional MDNNs by over four orders of magnitude, achieving a computational latency of 2.05 ns and a system-level energy efficiency of 0.83 TOPS/W, and reaching more than 86% accuracy across three functional prototypes—MNIST handwritten digit recognition, multi-user interference suppression, and real-time obstacle perception for drones—thereby validating the chip's capability to directly perform both digital image processing and in-situ electromagnetic information processing in the microwave domain.
This work fabricates a chip-scale microwave diffractive neural network (MDNN) in a GaAs semiconductor process, integrating cascaded couplers and phase shifters to implement a diffraction network within a millimeter-scale footprint, reducing the size of conventional MDNNs by over four orders of magnitude, achieving a computational latency of 2.05 ns and a system-level energy efficiency of 0.83 TOPS/W, and reaching more than 86% accuracy across three functional prototypes—MNIST handwritten digit recognition, multi-user interference suppression, and real-time obstacle perception for drones—thereby validating the chip's capability to directly perform both digital image processing and in-situ electromagnetic information processing in the microwave domain.
Mendeley Data Sep 16, 2026
This work assembles a corrosion inhibitor dataset from 5,597 publications using a multi-agent extraction pipeline, releasing a manually verified IE_datasets.xlsx, LLM-extracted json_extracted.zip, and IE_PH_4_materials.xlsx for model construction, with fields covering reference metadata, inhibitor name and composition, anodic/cathodic/mixed type, film mechanism, SMILES, corrosion material name, grade, composition, processing and heat treatment, corrosive medium, medium type, concentration and temperature, and test temperature, test time, inhibitor concentration, test method and inhibition efficiency percentage.
This work assembles a corrosion inhibitor dataset from 5,597 publications using a multi-agent extraction pipeline, releasing a manually verified IE_datasets.xlsx, LLM-extracted json_extracted.zip, and IE_PH_4_materials.xlsx for model construction, with fields covering reference metadata, inhibitor name and composition, anodic/cathodic/mixed type, film mechanism, SMILES, corrosion material name, grade, composition, processing and heat treatment, corrosive medium, medium type, concentration and temperature, and test temperature, test time, inhibitor concentration, test method and inhibition efficiency percentage.
A corrosion inhibitor dataset built from 5,597 publications
This work assembles a corrosion inhibitor dataset from 5,597 publications using a multi-agent extraction pipeline, releasing a manually verified IE_datasets.xlsx, LLM-extracted json_extracted.zip, and IE_PH_4_materials.xlsx for model construction, with fields covering reference metadata, inhibitor name and composition, anodic/cathodic/mixed type, film mechanism, SMILES, corrosion material name, grade, composition, processing and heat treatment, corrosive medium, medium type, concentration and temperature, and test temperature, test time, inhibitor concentration, test method and inhibition efficiency percentage.
This work assembles a corrosion inhibitor dataset from 5,597 publications using a multi-agent extraction pipeline, releasing a manually verified IE_datasets.xlsx, LLM-extracted json_extracted.zip, and IE_PH_4_materials.xlsx for model construction, with fields covering reference metadata, inhibitor name and composition, anodic/cathodic/mixed type, film mechanism, SMILES, corrosion material name, grade, composition, processing and heat treatment, corrosive medium, medium type, concentration and temperature, and test temperature, test time, inhibitor concentration, test method and inhibition efficiency percentage.
NVIDIA Technical Blog Sep 16, 2026
NVIDIA describes the deterministic execution model of the Groq 3 LPX low-latency accelerator within its Vera Rubin platform: the LPU compiler schedules compute and data movement down to the clock cycle, letting it predict per-cycle current demand and use Preemptive Power (PEP) and Clock Period Synthesis (CPS) to reduce voltage droop and shrink the voltage guardband, with internal testing showing over 60% less voltage drop, an estimated high single-digit percentage decrease in the baseline voltage that must be continually supplied, a potentially low-double-digit percentage reduction in power for the same workload, and up to 35x higher throughput per megawatt at the platform level versus the previous-generation GB200 NVL72 for 2T+ parameter models at long context and high interactivity.
NVIDIA describes the deterministic execution model of the Groq 3 LPX low-latency accelerator within its Vera Rubin platform: the LPU compiler schedules compute and data movement down to the clock cycle, letting it predict per-cycle current demand and use Preemptive Power (PEP) and Clock Period Synthesis (CPS) to reduce voltage droop and shrink the voltage guardband, with internal testing showing over 60% less voltage drop, an estimated high single-digit percentage decrease in the baseline voltage that must be continually supplied, a potentially low-double-digit percentage reduction in power for the same workload, and up to 35x higher throughput per megawatt at the platform level versus the previous-generation GB200 NVL72 for 2T+ parameter models at long context and high interactivity.
NVIDIA cuts voltage droop by over 60% with Groq 3 LPX deterministic execution to get more inference tokens per megawatt
NVIDIA describes the deterministic execution model of the Groq 3 LPX low-latency accelerator within its Vera Rubin platform: the LPU compiler schedules compute and data movement down to the clock cycle, letting it predict per-cycle current demand and use Preemptive Power (PEP) and Clock Period Synthesis (CPS) to reduce voltage droop and shrink the voltage guardband, with internal testing showing over 60% less voltage drop, an estimated high single-digit percentage decrease in the baseline voltage that must be continually supplied, a potentially low-double-digit percentage reduction in power for the same workload, and up to 35x higher throughput per megawatt at the platform level versus the previous-generation GB200 NVL72 for 2T+ parameter models at long context and high interactivity.
NVIDIA describes the deterministic execution model of the Groq 3 LPX low-latency accelerator within its Vera Rubin platform: the LPU compiler schedules compute and data movement down to the clock cycle, letting it predict per-cycle current demand and use Preemptive Power (PEP) and Clock Period Synthesis (CPS) to reduce voltage droop and shrink the voltage guardband, with internal testing showing over 60% less voltage drop, an estimated high single-digit percentage decrease in the baseline voltage that must be continually supplied, a potentially low-double-digit percentage reduction in power for the same workload, and up to 35x higher throughput per megawatt at the platform level versus the previous-generation GB200 NVL72 for 2T+ parameter models at long context and high interactivity.
Nature nanotechnology Sep 15, 2026
This work demonstrates wafer-scale monolithic 3D integration on 200-mm silicon wafers with three tiers of atomic-layer-deposited indium oxide (InOx)-based devices (more than 100,000 fabricated), including ferroelectric, enhancement-mode and depletion-mode field-effect transistors, achieving threshold voltage standard deviations as low as 0.04 V, average electron mobilities up to 91.6 cm²V⁻¹s⁻¹ and fully functional cross-tier circuits, and develops a four-tier 3D computing-in-memory accelerator targeting large-language-model workloads using a custom InOx process design kit, delivering 1.4× to 2.9× speed-up and comparable energy-delay product improvements over 2D baselines.
This work demonstrates wafer-scale monolithic 3D integration on 200-mm silicon wafers with three tiers of atomic-layer-deposited indium oxide (InOx)-based devices (more than 100,000 fabricated), including ferroelectric, enhancement-mode and depletion-mode field-effect transistors, achieving threshold voltage standard deviations as low as 0.04 V, average electron mobilities up to 91.6 cm²V⁻¹s⁻¹ and fully functional cross-tier circuits, and develops a four-tier 3D computing-in-memory accelerator targeting large-language-model workloads using a custom InOx process design kit, delivering 1.4× to 2.9× speed-up and comparable energy-delay product improvements over 2D baselines.
Monolithic 3D integration of atomic-layer-deposited oxide semiconductors on 200-mm silicon wafers
This work demonstrates wafer-scale monolithic 3D integration on 200-mm silicon wafers with three tiers of atomic-layer-deposited indium oxide (InOx)-based devices (more than 100,000 fabricated), including ferroelectric, enhancement-mode and depletion-mode field-effect transistors, achieving threshold voltage standard deviations as low as 0.04 V, average electron mobilities up to 91.6 cm²V⁻¹s⁻¹ and fully functional cross-tier circuits, and develops a four-tier 3D computing-in-memory accelerator targeting large-language-model workloads using a custom InOx process design kit, delivering 1.4× to 2.9× speed-up and comparable energy-delay product improvements over 2D baselines.
This work demonstrates wafer-scale monolithic 3D integration on 200-mm silicon wafers with three tiers of atomic-layer-deposited indium oxide (InOx)-based devices (more than 100,000 fabricated), including ferroelectric, enhancement-mode and depletion-mode field-effect transistors, achieving threshold voltage standard deviations as low as 0.04 V, average electron mobilities up to 91.6 cm²V⁻¹s⁻¹ and fully functional cross-tier circuits, and develops a four-tier 3D computing-in-memory accelerator targeting large-language-model workloads using a custom InOx process design kit, delivering 1.4× to 2.9× speed-up and comparable energy-delay product improvements over 2D baselines.
Chemical Communications Sep 15, 2026
This review organizes lithium-sulfur battery catalyst research around the fundamental chemistry of sulfur conversion and its rate-limiting steps, links catalyst modulation strategies to descriptors, groups descriptors into electronic, thermodynamic, and structural categories with their property-performance relationships, and points toward universal descriptors as well as the potential roles of in situ characterization, computational modeling, and artificial intelligence in descriptor construction and the design of highly active catalysts.
This review organizes lithium-sulfur battery catalyst research around the fundamental chemistry of sulfur conversion and its rate-limiting steps, links catalyst modulation strategies to descriptors, groups descriptors into electronic, thermodynamic, and structural categories with their property-performance relationships, and points toward universal descriptors as well as the potential roles of in situ characterization, computational modeling, and artificial intelligence in descriptor construction and the design of highly active catalysts.
Rational design of advanced electrocatalysts based on reactivity descriptors for high-performance lithium-sulfur batteries
This review organizes lithium-sulfur battery catalyst research around the fundamental chemistry of sulfur conversion and its rate-limiting steps, links catalyst modulation strategies to descriptors, groups descriptors into electronic, thermodynamic, and structural categories with their property-performance relationships, and points toward universal descriptors as well as the potential roles of in situ characterization, computational modeling, and artificial intelligence in descriptor construction and the design of highly active catalysts.
This review organizes lithium-sulfur battery catalyst research around the fundamental chemistry of sulfur conversion and its rate-limiting steps, links catalyst modulation strategies to descriptors, groups descriptors into electronic, thermodynamic, and structural categories with their property-performance relationships, and points toward universal descriptors as well as the potential roles of in situ characterization, computational modeling, and artificial intelligence in descriptor construction and the design of highly active catalysts.

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