Raphael Viera

Physical hardware security evaluation has depended on a person choosing each laser fault-injection position, power and timing. A large-language-model agent now links firmware reverse engineering, chip imagery and experimental decisions into a closed loop, choosing the next shot inside human-approved safety bounds. On an ATmega328P it produced a skipped load instruction and a wrong-PIN acceptance confirmed by a separate state read; on an Artix-7 FPGA the same workflow extended to ciphertext-error classification in programmable logic.

Physical hardware security evaluation has depended on a person choosing each laser fault-injection position, power and timing. A large-language-model agent now links firmware reverse engineering, chip imagery and experimental decisions into a closed loop, choosing the next shot inside human-approved safety bounds. On an ATmega328P it produced a skipped load instruction and a wrong-PIN acceptance confirmed by a separate state read; on an Artix-7 FPGA the same workflow extended to ciphertext-error classification in programmable logic.