Peide D Ye

This work demonstrates wafer-scale monolithic 3D integration on 200-mm silicon wafers with three tiers of atomic-layer-deposited indium oxide (InOx)-based devices (more than 100,000 fabricated), including ferroelectric, enhancement-mode and depletion-mode field-effect transistors, achieving threshold voltage standard deviations as low as 0.04 V, average electron mobilities up to 91.6 cm²V⁻¹s⁻¹ and fully functional cross-tier circuits, and develops a four-tier 3D computing-in-memory accelerator targeting large-language-model workloads using a custom InOx process design kit, delivering 1.4× to 2.9× speed-up and comparable energy-delay product improvements over 2D baselines.

This work demonstrates wafer-scale monolithic 3D integration on 200-mm silicon wafers with three tiers of atomic-layer-deposited indium oxide (InOx)-based devices (more than 100,000 fabricated), including ferroelectric, enhancement-mode and depletion-mode field-effect transistors, achieving threshold voltage standard deviations as low as 0.04 V, average electron mobilities up to 91.6 cm²V⁻¹s⁻¹ and fully functional cross-tier circuits, and develops a four-tier 3D computing-in-memory accelerator targeting large-language-model workloads using a custom InOx process design kit, delivering 1.4× to 2.9× speed-up and comparable energy-delay product improvements over 2D baselines.