Monolithic 3D integration of atomic-layer-deposited oxide semiconductors on 200-mm silicon wafers

Wafer-scale monolithic 3D integration of three tiers of atomic-layer-deposited InOx-based devices on 200-mm silicon wafers, with more than 100,000 devices fabricated, including ferroelectric, enhancement-mode and depletion-mode field-effect transistors. Prior monolithic 3D integration has often relied on other material systems or smaller-scale demonstrations; this work combines atomic-layer-deposited InOx with wafer-scale 3D stacking and covers multiple device types simultaneously. Based on fabrication and electrical characterization of more than 100,000 devices on 200-mm wafers, reporting threshold voltage standard deviations as low as 0.04 V and average electron mobilities up to 91.6 cm²V⁻¹s⁻¹.

Fully functional cross-tier circuits were achieved, indicating that the stacked tiers can operate together. Functional cross-tier circuits advance monolithic 3D integration from the single-device level to the circuit level. The text reports 'fully functional cross-tier circuits,' but the abstract does not give specific numbers for circuit scale or yield.

A four-tier 3D computing-in-memory accelerator targeting large-language-model workloads was developed using a custom InOx process design kit, delivering 1.4× to 2.9× speed-up and comparable energy-delay product improvements over 2D baselines. It combines the atomic-layer-deposited InOx monolithic 3D integration platform with a computing-in-memory accelerator design and evaluates it for large-language-model workloads. The speed-up and energy-delay product improvements come from comparison with 2D baselines; the specific benchmark configuration and simulation or measurement conditions are not detailed in the abstract.

The results apply to atomic-layer-deposited InOx monolithic 3D integration on 200-mm silicon wafers, aimed at AI hardware and advanced electronics scenarios requiring vertically stacked logic and memory devices; the accelerator evaluation targets large-language-model workloads and compares against 2D baselines.

The abstract does not specify the scale and yield of cross-tier circuits, the benchmark configuration and evaluation mode (simulation or measurement) of the four-tier accelerator, the specific values of energy-delay product improvement, or the device type and test conditions corresponding to the 0.04 V threshold voltage standard deviation; these are open questions a reader would still watch when judging platform maturity.