Chiplet design space stops being a black box: LLM sets direction, Bayesian optimization does the numbers

Chiplet design space exploration gains a path for writing microarchitectural experience into the search: the large language model no longer predicts which configuration is best, but at each step says whether a parameter should rise, fall, or stay, and Bayesian optimization searches numerically inside that direction. Earlier approaches either treated the system as a black box and searched on statistical correlation, or injected expert knowledge through fixed rules and biased initialization, which limits efficiency when cycle-accurate simulation is expensive and samples are few. On the 3D chiplet dataset hypervolume rises from 0.8210 for LLM-DSE to 0.8356, a change the source table labels 13.3%; on the 2.5D dataset, excluded from fine-tuning, it rises from 0.7809 to 0.8051, labeled 9.3%.

The directional policy comes from a structured reasoning procedure: locate the main bottleneck of the current anchor design, predict the effect of raising or lowering related parameters, then reflect on the previous iteration's new evaluations and hypervolume change to revise the direction. Asking the model to predict optimal configurations directly is unreliable, because chiplet design space involves complex numerical trade-offs and the model may give biased recommendations for unfamiliar chiplet designs. The policy is produced by fine-tuning Qwen2.5-7B-Instruct with group relative policy optimization, under a reward combining reasoning format, answer format and validity, and exploration gain with weights 0.2, 0.2, and 0.6, in a one-time offline run of about 20 hours on eight NVIDIA A800 GPUs.

The policy enters the acquisition function as a soft prior: acquisition values of candidates inside the policy-consistent subspace are raised, without replacing Bayesian optimization's uncertainty-based candidate selection. Standard expected hypervolume improvement ranks candidates only by the numerical model and does not distinguish which regions deserve earlier evaluation. Experiments use a design space of 11 parameters and 18,432 configurations, where each design evaluation takes about 10 minutes of simulation and generating the full dataset consumed 6,144 CPU core-hours; the 3D dataset samples 2,000 configurations and builds 6,000 prompts, split after deduplication and filtering into 4,800 training and 1,200 validation samples.

The report covers architectural-level design space exploration for 2.5D and 3D CPU-GPU heterogeneous chiplets, optimizing power, cycles per instruction, and interconnect delay under an architectural-level thermal feasibility constraint. The thermal model is used for early-stage architectural screening rather than signoff-level thermal verification. It suits researchers and engineers working on chiplet architecture exploration and multi-objective optimization tooling.

Thermal evaluation uses a lightweight steady-state model intended for early screening. The 2.5D task is excluded from fine-tuning, so its performance comes from transfer evaluation. Policy guidance enters as a soft prior, and the acquisition boost is set according to an empirical scale. The source table labels the 3D hypervolume change from 0.8210 to 0.8356 as 13.3%, a label that is not consistent with those two values; the report keeps the label and the raw values side by side.