Skip to main content
Search

# Hardware-in-the-Loop Testing

1 related articles

Subscribe to updates
  1. arXiv

    A PMSM digital twin that relearns its own step: FPGA runs the network, and a shifted machine is re-approached in 94 seconds

    Real-time digital twins of permanent magnet synchronous machines have relied on offline-identified parameters or finite-element flux look-up tables, which must be regenerated when the machine changes. The Inferencer-in-the-Loop architecture has a field-programmable gate array execute a physics-guided network while a GPU retrains it from reference data, switching weights only after validation. Across damper circuits, shifted parameters and an FEA-calibrated saturated machine, one kernel form reaches average normalized mean absolute errors of 0.19%–0.67% at measured kernel latencies of 0.30–0.34 microseconds; on a 200-W drive, a residual form gives errors of 5.9%–9.4% of measured RMS over six held-out runs.

You’re all caught up