No GPUs needed to plan LLM serving: BLIS simulates the full pipeline on CPU and holds a 300 ms TTFT SLO on four H100s
BLIS is a deterministic, CPU-only discrete-event simulator that models the whole LLM inference serving pipeline, including admission, routing, scheduling, prefill/decode execution, KV-cache management, and preemption, reaching 6.7% median end-to-end error across 36 experiments while running about 200 times faster than real execution.