Analog layout stops fixing sizing before routing: CASCoDe hands structural decisions to an LLM agent, and all 20 amplifiers come out DRC- and LVS-clean

An analog circuit's layout area and post-layout performance depend on joint decisions between sizing and physical structure, yet existing flows fix the physical search space before the controller runs, so extracted electrical results after routing cannot revise upstream choices. CASCoDe turns those expert decisions into executable, revisitable actions so one loop runs from a sizing candidate pool to a verified GDS. In prior automated flows sizing is fixed on entry to layout and post-layout results are not fed back to earlier decisions; row-based synthesis and post-layout-driven sizing bring extracted performance into parameter optimization, but exploration stays bounded by a prescribed row fabric or the layout generator's physical choices. On 20 SKY130 amplifiers (ten one-stage, five two-stage, five three-stage, 6–39 devices each), CASCoDe is the only flow giving a DRC- and LVS-clean routed layout for all 20 circuits, while APPlace, MAGICAL and ALIGN are clean on 15, 0 and 1 circuits.

The agent acts not on tool parameters but on structural objects such as floorplan form, in-row device arrangement, device shape and routing configuration, so a localized diagnosis can become a targeted layout edit. The action space is layered as sizing candidate pool, structural floorplan, intra-row refinement and routing-attempt selection; the agent runs feedback-guided tree search over it and writes circuit-specific floorplan generators and helper scripts. A thin execution layer of interface adaptations over unmodified tools makes every action land at exact coordinates and be judged by DRC, LVS and RC-extracted simulation; against APPlace on identical PCells, area falls 59–85% (mean 71%), mean device density rises from 0.39 to 0.74, and mean post-layout FoM is 6.92 versus 6.76 for APPlace, 6.04 for MAGICAL and 6.52 for ALIGN.

The demonstrated scope is 20 amplifiers in SKY130 spanning single-, two- and three-stage topologies, with 6–39 devices each and MIM compensation capacitors on the two- and three-stage designs; every layout is judged by DRC, LVS, functional checks and RC-extracted post-layout simulation under fixed testbenches and fixed performance requirements. The ablation adds an LDO and a comparator, and the agent-model sensitivity study runs on the same five circuits.

The delivered layouts still fall short of carefully hand-crafted ones, the agent can only combine predefined actions with the bridging tools it writes, and the objective covers routed area and post-layout performance under a fixed testbench set, so practices DRC, LVS and these metrics do not capture, such as gradient-aware matching, shielding of sensitive nets and reliability, are not explicitly optimized. A run averages 61 trials, 94 minutes and 0.42 M tokens, rising to 233 minutes for the three-stage class, so cost grows with circuit size; the first layout beating every baseline in area and DRC count appears after 11 minutes on average, about 12% of the budget, and further refinement is paid for with additional trials.