Microwave diffractive neural network chips: sensing and computing on a millimeter-scale GaAs chip

It proposes and fabricates a chip-scale microwave diffractive neural network (MDNN) that integrates cascaded couplers and phase shifters in a GaAs semiconductor process, compressing the diffraction network into a millimeter-scale package. Where optical diffractive networks have been constrained by fabrication and scalability limits and metasurface microwave systems remain bulky, this work reduces the size of conventional MDNNs by over four orders of magnitude. The evidence comes from an actually fabricated GaAs chip and its stated size comparison, i.e., device-level implementation evidence; the text does not give a specific chip area value or process-node details.

The chip achieves a computational latency of 2.05 ns and a system-level energy efficiency of 0.83 TOPS/W. It provides quantifiable low-latency, low-power operating metrics for electromagnetic diffractive neural networks, supporting their positioning as an ultra-low-power, low-latency AI inference pathway. Latency and energy efficiency are reported as system-level measured metrics, i.e., measured data from a single prototype chip, without cross-device or cross-batch statistics.

Versatility is demonstrated through three functional prototypes—MNIST handwritten digit recognition, multi-user interference suppression, and real-time obstacle perception for drones—all achieving more than 86% accuracy. The same chip architecture is used both for digital image processing and for in-situ electromagnetic information processing in the microwave domain, indicating the architecture is not limited to a single task type. The evidence is the accuracy results of three prototype experiments (all above 86%), i.e., demonstrative validation; the text does not give per-task accuracy values, dataset sizes, or comparison baselines.

The result targets settings that need inference and electromagnetic information processing directly in the microwave domain, such as digital image recognition, multi-user interference suppression, and real-time obstacle perception for drones; its value lies in moving the diffraction network from benchtop or metasurface systems onto a millimeter-scale chip, making ultra-low-latency, low-power inference possible at the device level. For readers, this means it is worth watching how the architecture performs in larger-scale networks, additional task types, and integration with other microwave front ends.

What is currently available is abstract-level information, lacking details such as chip area, process node, number and scale of network layers, per-task accuracy values and dataset sizes, comparison baselines, and the measurement conditions for energy efficiency and latency; therefore the magnitude of the performance advantage and its applicable boundaries still need to be judged against the original figures and tables. In addition, the three prototypes are demonstrative tasks, so how the architecture performs on more complex tasks and larger-scale networks, and the practical constraints of integrating it with other microwave front ends, remain open questions worth continued observation.