A polymer memristor probabilistic computer: four p-bits sample Bayesian posteriors in hardware, with statistics inside the finite-sample range of ideal samplers

The entropy source of a probabilistic computer is now a soft material: four p-bits made from spin-coated conjugated-polymer memristors form a closed-loop sampling hardware network used for Bayesian posterior inference rather than optimization. Earlier hardware networks of physical p-bits were all built from inorganic devices, including magnetic tunnel junctions, ferroelectric tunnel junctions and oxide memristors, and addressed optimization, logic or learning a fixed mapping. On three odor-identification tasks with only sixteen possible answers, the KL divergence between sampled distribution and exact posterior fell inside the 95% range of 1000 simulated ideal-p-bit runs at every 100-sweep checkpoint in eight of nine runs, and at 99 of 100 checkpoints in the ninth.

Each p-bit draws its randomness from the random time variation of the polymer film's resistance, and the input is applied only by shifting the comparator reference while the memristor supply stays fixed throughout sampling. Earlier inorganic networks typically drove devices with write pulses, or had a microcontroller apply each input through a digital-to-analog converter to a transistor in series with the junction. The four devices operated at levels from about 0.1 V to about 1.0 V with transition widths from about 10 mV to 110 mV, yet once expressed through tracked parameters all four collapsed onto one logistic curve, following the ideal line from about 0.001 to 0.999.

Changing biases and couplings in software lets the same circuit and controller sample competing, degenerate and cooperative posteriors in succession without any hardware modification. Most earlier p-bit demonstrations targeted a single task or fixed mapping and were judged by histograms, optimality gaps or success probabilities. Fifteen of 18 runs, covering all three tasks with original and new readings, ran consecutively without intervention over about 50 hours; individual memristor operating levels shifted by several hundred millivolts and noise widths changed by factors up to six, yet every run stayed within the ideal-p-bit range.

On the invertible AND gate, the standard benchmark of p-bit networks, the freely running network spent 96% of sweeps on the four truth-table rows in nearly equal shares, matching the 96% of ideal p-bits. Earlier magnetic p-bit work adjusted a parameter until the Boltzmann law matched measured counts, whereas here temperature was set before the runs and measured frequencies were compared directly with the exact distribution. With both inputs clamped to 1 the output took state 1 in 95% of sweeps, and with the output clamped to 0 the network spent 98% of sweeps on the three consistent input pairs, with the KL divergence inside the ideal-p-bit range in both modes.

The demonstration is limited to four p-bits, sixteen-state odor-identification posteriors and the invertible AND gate, running on ITO/pB6CC/Al memristors spin-coated on glass with breadboard circuitry and couplings computed by a Python controller through four microcontrollers. The authors list speed, scale and integration as next steps and note that larger networks need additional circuits but no change to the controller.

The authors state that the online tracking learning rates are heuristic and the tracked chain is not expected to converge exactly to the posterior, so the KL divergence levels off at a value that decreases with the learning rates; in simulations of ideal p-bits with the same online calibration, this theoretical discrepancy lies two to three orders of magnitude below the KL values reached after 10 000 sweeps. Extreme tail probabilities may not follow the logistic law, so only states whose target probability lies between 1% and 99% update the midpoint and slope estimates.