CircuitGate adds global primary-input support and reconvergence modeling to AIG representation, cutting equivalent-gate MAE by 21.7% on ForgeEDA

CircuitGate moves AIG representation learning from local gate-level message passing toward circuit-level functional modeling: each node carries EDA-native context beyond gate type, including logic level, transformed fanout, sink status and PI-support coverage, and the model explicitly encodes global PI-support sets separated by inversion parity. Existing GNN methods (the DeepGate series, FGNN, FuncGNN, PolarGate, HOGA, WideGate and others) propagate information mainly along local connectivity, so finite-hop message passing struggles to preserve global PI dependencies across deep logic hierarchies; this work compresses variable-size support sets into fixed-width representations injected as a layer-invariant circuit-level prior. On ForgeEDA (83,155 circuit instances derived from 4,450 AIGs across 1,189 open-source designs), removing PI-dependency encoding degrades MAE by 34.4%, the largest single-component degradation in the ablation; removing reconvergence modeling degrades it by 29.6%.

The work characterizes reconvergent fanins through PI-support overlap and uses a dependency gate to adaptively control how global PI information participates in node updates, while preserving the original AIG connectivity. Prior message passing aggregates fanins with shared PI support as independent structural neighbors, leaving shared-input dependencies only indirectly reflected; here a six-dimensional reconvergence descriptor (reconvergence presence, Jaccard overlap, overlap coefficient, log-scaled shared-support size, normalized fanin-depth imbalance, and same- versus opposite-parity overlap contrast) explicitly conditions local propagation. On ForgeEDA the merge-gate reconvergence formulation reaches an MAE of 0.0433, 4.6% lower than the binary-flag formulation and 22.8% lower than omitting reconvergence modeling entirely.

The training objective augments task supervision with logic-inspired regularization: NOT complementarity for explicit NOT operations and Fréchet probability bounds for two-input AND nodes that require no fanin-independence assumption, encouraging consistent representations for functionally equivalent circuits under synthesis-induced structural change. The regularization targets the tension that functionality-preserving synthesis transformations (resyn2, dc2, rewrite, refactor) can substantially alter topology while Boolean functionality is unchanged, constraining Boolean probability relations that hold across structural realizations rather than relying on implementation-specific topology. On 20 transformed ForgeEDA test circuits, CircuitGate attains the highest CKA under all four transformations (resyn2 0.7933, dc2 0.7866, rewrite 0.8775, refactor 0.8789) and the lowest equivalent-gate MAE on the same matched pairs.

On the joint accuracy-efficiency trade-off, CircuitGate reaches an equivalent-gate MAE of 0.0433 with 2.8170M parameters and 12.4393 ms neural inference latency, and the best AEC (1.0275), while one-time preprocessing is validated on complete circuits. Relative to MGVGA, MAE drops 23.1% with only a 1.3% latency increase; relative to the larger DeepGate3 (4.7272M, 73.2356 ms) and DeepGate4 (4.6465M, 172.2620 ms), it is favorable on both latency and accuracy. Latency is measured on a fixed subset of 200 test circuits at batch size one and excludes one-time graph preprocessing; preprocessing on the largest complete circuit with 525,762 nodes and 733,211 edges takes 14.03 s for feature construction and 14.89 s input-to-cache with a peak RSS of 2.73 GiB.

The results target AIG representation learning over two-input AND gates with complemented edges, in settings such as logic synthesis, formal verification and optimization that need node-level functional representations, for example equivalent-gate identification and signal-probability prediction. The value of the method is tested directly under functionality-preserving synthesis transformations (resyn2, dc2, rewrite, refactor), so the most immediate beneficiaries are settings that must keep representations consistent across different synthesis realizations. The efficiency conclusions apply at the tested scale: neural inference is measured on a 200-circuit test subset at batch size one, and one-time preprocessing is completed on the largest complete circuit with 525,762 nodes and 733,211 edges at a peak RSS of 2.73 GiB. Cross-dataset conclusions are limited to the zero-shot ForgeEDA-to-OpenABC transfer setting.

Several open questions remain for a careful reader. PI support is described as a structural approximation of exact Boolean functional support, and a PI may appear in both the even- and odd-parity support sets; the text does not bound how widely that approximation holds across circuit structures. Reconvergence descriptors are constructed only for two-input AND nodes, with all other nodes using a zero descriptor, so what this implies for circuits dominated by other gate types remains to be examined. The ForgeEDA test set has a positive-pair rate of only 0.464648%, so absolute AP values should be read together with each benchmark's positive rate. Hyperparameter analysis shows that overly strong logic regularization or insufficient propagation depth degrades performance noticeably, so the default configuration is a favorable operating point on the evaluated metrics rather than a unique optimum. In addition, this is a fast-parse version in which formulas and some table values are not fully rendered in the text, so restatement of exact formula forms and some numbers is limited to what the readable body supports.