RFChipAgent's multi-agent flow automates topology selection, schematic and testbench generation, and closed-loop sizing for a GF22FDSOI 60 GHz wideband LNA, with Trial #174 meeting every specification

It presents and validates what the authors describe as the first multi-agentic AI flow for end-to-end analog/RF circuit design automation, spanning knowledge ingestion, topology selection, schematic and testbench generation, simulator-in-the-loop optimization, and trust-scored knowledge accumulation. Prior work such as EVA and multi-agent generative synthesis frameworks focuses mainly on topology generation or inverse design, without a complete flow spanning knowledge ingestion, schematic generation, simulation-driven optimization, and trusted knowledge accumulation. Validated end-to-end on a GF22FDSOI 60 GHz wideband LNA, exercising every stage of the loop, with reported trials that cleared the trust threshold and a full design-variable table.

A provenance-preserving RAG with per-document FAISS indexing keeps retrieved topology descriptions, performance metrics, and design insights explicitly traceable to their source documents, reducing cross-document attribution errors. Unlike merged-index RAG systems that rely on a single vector database spanning all documents (such as MuaLLM-style approaches), this design builds a temporary combined search space only at query time while retaining each chunk's source-document identity. The knowledge base comprises ten LNA design references, and the retrieved priors directly influenced the topology agent's architectural decisions, such as selecting a transformer-based matching network for 60 GHz wideband operation.

Per-trial physical-validity gates run before objective evaluation: a DC operating-point check discards trials with any device outside saturation or subthreshold operation, and a stability check computes the Edwards–Sinsky K-factor from 1 Hz to 90 GHz, rejecting trials with K below 1 or a global K above 0 dB. A scalar-objective optimizer cannot distinguish a physically valid low-performing design from a physically invalid one that violates fundamental circuit requirements; these gates prevent infeasible solutions from consuming optimization budget. Reported performance numbers are drawn only from trials that cleared both the physical-validity gates and the trust threshold, not from raw simulator output.

A trust-score gated database weights execution integrity at 70% and data provenance at 30%, admits only qualifying trials, and prefers regions of the design space that historically produced good outcomes via a likelihood ratio of two non-parametric density estimates over good and bad sets. This makes the database auditable and reusable across campaigns, and lets the LLM perform deterministic diagnostics and what-if analysis between campaigns, for example distinguishing a physical boundary from a nonphysical one for boundary-pinned variables. Execution integrity is a weighted sum of verification indicators including PSF availability, nonzero metrics, full-band stability extraction, and optional corner/EM coverage.

The flow targets analog/RF circuit designers who must simultaneously satisfy gain, noise, return loss, in-band ripple, and power metrics in a tightly coupled design space, especially for mm-wave wideband circuits. The validation scenario here is a two-stage 60 GHz wideband LNA in GF22FDSOI, with specifications on minimum gain, maximum noise figure, maximum return loss, in-band ripple, and power consumption; the topology agent accordingly selects a neutralized-differential-pair second stage cascaded with a common-source degenerated first stage, matched with an input auto-transformer and two transformer-based interstage/output networks. The flow is designed to run under human supervision, and the agent architecture is described as extensible to other analog/RF circuit classes through block-specific rules. The trust-gated database is auditable and reusable across campaigns, and between-campaign LLM diagnostics can advise on search stagnation, boundary-pinned variables, and the sigmoid penalty region of unmet specifications.

Validation currently centers on a single circuit class (LNA) and a single technology node (GF22FDSOI) in a 60 GHz wideband scenario, so behavior when extended to other analog/RF circuit classes and processes remains to be seen. Reported performance numbers come from trials that cleared the physical-validity gates and trust threshold; how far they differ from raw simulator output, and the sensitivity of the trust score to its 70%/30% weighting of execution integrity and data provenance, are directions a careful reader may continue to watch. The cost and wall-clock figures (about 2 hours, $156.20) correspond to this one design campaign, and the scale under different specifications, variable dimensions, or simulation settings still needs more cases to confirm. In addition, this text is a fast parse in which equations (1) through (5) and some table cells are not fully expanded; readers who need the exact objective and trust-score forms should consult the original figures and tables.