PrefixAgent uses a two-phase LLM agent with e-graph trajectory fine-tuning to cut 64-bit prefix adder area to 938 µm², 11.3% below the strongest baseline
Synopsis
The work proposes PrefixAgent, a two-phase large-language-model-driven framework for prefix adder optimization: in Phase I a fine-tuned large reasoning model iteratively optimizes the backbone via regroup tool calls, and in Phase II it performs local timing repair with level-opt, fanout-opt, and node clone tools; the authors use e-graph equality saturation and explanation to generate interpretable rewrite trajectories as supervision data, and under the NanGate45 and OpenROAD flow PrefixAgent produces smaller-area adders than DP, MCTS, PrefixRL, CircuitVAE, and PrefixGPT in nearly all configurations, achieving up to 11.3% area reduction over the best baseline at 64 bits and also improving area in a commercial flow and a 256-PE systolic array.
Fig. 1. The two-phase framework in PrefixAgent.
· Page 2Interpretation
The prefix adder design problem is decomposed into backbone generation and local structure refinement, where the backbone is defined as the subgraph computing the MSB carry with N−1 nodes, compressing the exponential design space into a single Catalan number. Prior methods either rely on regular structures or search/generate over the full prefix graph; this work is the first to restrict optimization to the backbone and to show that backbone optimization corresponds one-to-one with e-graph rewriting. The paper derives backbone node count S_B = N−1 and auxiliary node count S_A = N−1−L_B, and states that the 16-bit design space drops from about 10^48 to 10^6; the link between backbone and the zero-deficiency condition S+L=2n−2 is grounded in Snir's theorem.
E-graph equality saturation, a timing-aware cost function, and the egg explainer are used to automatically generate large-scale, interpretable backbone optimization trajectories as supervision data for fine-tuning the large reasoning model. Prior training data came from random generation or perturbation, which struggles to produce meaningful optimization trajectories; this work maps the associativity rewrite rule R1 to the regroup operation and extracts rewrite sequences via the egg explainer as interpretable trajectories. The paper reports trajectory statistics from 8 to 64 bits (e.g., 64-bit: 16 profiles, 90 trajectories, 5760 regroup steps) and shows the timing-aware cost beats AST-depth and random baselines on 16-bit backbones in critical-path delay (e.g., profile 1: 0.4862 ns vs 0.5684 ns and 0.6692 ns).
PrefixAgent generates smaller-area prefix adders in nearly all configurations under both uniform and non-uniform arrival times, with the advantage widening at larger bit-widths. Compared with DP, MCTS, PrefixRL, CircuitVAE, and PrefixGPT, this work is the first LLM-based approach to scale to 64-bit designs and Pareto-dominates all baselines at 64 bits. In the non-uniform arrival time table, PrefixAgent achieves the smallest area in seven of eight configurations, with up to 11.3% area reduction over the best baseline at 64 bits; under uniform arrival time it Pareto-dominates all baselines at 64 bits; all generated adders pass ABC equivalence checking.
In a commercial physical design flow and a 256-PE systolic array, replacing synthesis-tool default adders with PrefixAgent-generated adders reduces area and improves critical-path delay. Prior work mostly stayed within academic open-source flows; this work extends evaluation to a 32 nm commercial toolchain and an accelerator-level setting. In the commercial flow table, PrefixAgent has smaller area than the commercial synthesis tool under both LSB-first and Random profiles (e.g., 64-bit LSB-first: 1574.76 µm² vs 1639.09 µm²); the systolic array improves both area and delay under OpenROAD and commercial flows at 8-bit and 16-bit.
Perspective
The result targets digital circuit designers who need to optimize prefix adders under given input arrival times and target delays, and it applies to the NanGate45 open library with the OpenROAD flow plus a 32 nm commercial physical implementation flow; the authors note the backbone-plus-e-graph-trajectory supervision paradigm can be reused for multiplier compressor-tree templates and broader datapath RTL/netlist optimization, making it most directly valuable to readers working on arithmetic datapaths and accelerator design.
Readers should still watch: 54 bits is the only unseen bit-width evaluated, and both arrival-profile families appear in the training distribution, so the results do not establish generalization to arbitrary bit-widths or unseen profile families; the transfer of the backbone-plus-e-graph-trajectory paradigm to multipliers and broader datapaths is currently only an outlook from the authors, with no experiments; and the correspondence between backbone optimization and e-graph rewriting relies on the specific associativity rewrite rule, so whether it holds under other structural constraints is worth further observation.
