Alibaba Damo's XuanTie unveils automotive roadmap: E908A is billed as the first RISC-V CPU IP to reach both ASIL-B and ASIL-D
Synopsis
At the RISC-V China Summit in Shenzhen, Alibaba Damo Academy's XuanTie unit released the automotive-enhanced processor E908A, which it describes as the first RISC-V CPU IP to meet both ASIL-B and ASIL-D standards, with a single-point fault metric (SPFM) above 90% for the first time in the industry, aimed at safety islands, domain controllers and automotive gateways. Damo also published its first autonomous-driving and embodied-intelligence product roadmap, with the next-generation C950A targeting five times the performance of existing RISC-V automotive products. RISC-V had mainly been framed as an open instruction-set architecture advancing in general-purpose and server fields; automotive safety grades are a new threshold it is entering.
Interpretation
Alibaba Damo's XuanTie pushed RISC-V processors into the automotive-safety domain with the automotive-enhanced E908A, positioned as a real-time computing base for safety islands, domain controllers and automotive gateways. RISC-V had been described as an open instruction-set architecture rapidly catching up with X86 and Arm and entering high-value fields such as AI and servers; automotive processors are a newly entered direction for XuanTie. According to the summit release, E908A is the first RISC-V CPU IP to reach both ASIL-B and ASIL-D standards, and its single-point fault metric SPFM exceeds 90% for the first time in the industry.
Alongside E908A, Damo published an autonomous-driving and embodied-intelligence product roadmap, in which the next-generation C950A carries a target performance figure. Existing RISC-V automotive products serve as the performance reference for this roadmap, and C950A targets five times their performance. The fivefold figure is the roadmap's target performance, not a measured production result.
On the server and AI side, the XuanTie C950 uses the XT-LINK multi-core interconnect product to improve multi-core performance linearity, with whole-series optimization across general compute, matrix acceleration, memory bandwidth and software co-design. Damo says C950 set a global RISC-V performance record when released in March and now serves as the innovation base for high-performance RISC-V technology. Across four Agentic workloads, C950 improves on mainstream traditional-architecture processors by more than 10%; running Qwen3.8-Flash-Next, released in August, it reaches an inference speed of 43 tokens per second.
Perspective
The report covers the automotive product roadmap released by Alibaba Damo's XuanTie at the RISC-V China Summit, E908A's safety grades and SPFM figure, and C950's performance on Agentic workloads and Qwen3.8-Flash-Next; it is aimed at researchers and engineers following RISC-V architecture and automotive chips.
C950A's fivefold performance is a roadmap target, and the material does not state its test conditions or timeline; E908A's ASIL grades and SPFM figure come from the summit release, and the material does not give the corresponding certification or test details.