ATLAS maps feasible-region topology with Mapper graphs to reach 100% success on four analog sizing benchmarks with fewer SPICE simulations

ATLAS brings topological data analysis into the query mechanism of analog circuit sizing: it builds a Mapper graph over the surrogate-predicted near-feasible point cloud and uses the zeroth Betti number to estimate the number of connected regions of the feasible set, obtaining a map of the feasible landscape before any truly feasible point has been observed. Existing BO methods (WEIBO, MACE, TuRBO, SCBO and others) treat the design space as structurally homogeneous in their acquisition functions, ignoring that the feasible set may fragment into disconnected regions due to operating-regime transitions, conflicting specification trade-offs, and nonconvex device physics; the authors state this is the first work to apply TDA to analog circuit design automation. The method is specified in full: a Latin hypercube candidate pool is thresholded softly by feasibility score to form the feasible set, points are normalized, and a Mapper graph is assembled from cover intervals with DBSCAN as the local clustering subroutine; the authors note DBSCAN acts only locally and that ATLAS consumes the graph's connected-component structure, with one parameter setting serving every circuit, seed, and iteration.

A topological sensitivity score classifies candidates as bridge, frontier, or interior, with bridge and frontier points receiving an exploration bonus; a region-visit discount scales down scores in heavily sampled regions, and centroid-guided local search distributes local candidates across region centroids in proportion to under-exploration. These three mechanisms are unified into a single acquisition function that decays to weighted EI as the budget progresses and strictly recovers WEIBO when the topological sensitivity and discount are disabled, making ATLAS a strict generalization of WEIBO. Ablations on TSA remove one mechanism at a time: full ATLAS scores 10/10, removing centroid guidance 6/10, removing decay 9/10, removing topological sensitivity 7/10, and removing the region discount 9/10; the authors note that because FSD averages only over successful runs, censored failures make some variants look faster than they are, and that SR rather than FSD separates these rows.

Across four benchmark circuits ATLAS achieves the highest or tied-highest success rate: 100% on CMA (10 parameters, 6 specs) where the only successful baseline, CMA-ES, reaches 10% and the other six baselines score 0%; 100% on TSA versus SCBO 60%, CMA-ES 40%, and MACE 20%; and 100% on Comp and LDO tied with CMA-ES or SCBO but converging faster. The authors attribute the gap to the degree of topological fragmentation: SCBO's adaptive trust regions succeed on the relatively connected LDO but fail completely on the severely fragmented CMA. Each circuit is run on 10 random specification targets with a 500-evaluation SPICE budget and early stopping upon finding a feasible design, with identical initial random samples across methods; the case study reports that CMA peaks at over 200 Mapper regions while TSA peaks at only about 50, and that the region count decreases as specification satisfaction improves.

TDA overhead is controlled: Mapper construction, classification, and bookkeeping are refreshed every few iterations and cached, adding at most 0.04 s (under 2%), while region assignment and discounting add 0.03–0.16 s, for total controlled overhead of 1–17% that would be relatively smaller with slower industrial SPICE. This addresses the practical concern that topological analysis might impose prohibitive computational cost, indicating that the bottleneck remains the number of simulations rather than per-iteration wall-clock time. Table 4 breaks down mean per-iteration wall-clock time per circuit, where the simulation time is open-source ngspice runtime for these netlists, which the authors explicitly state is not extracted-layout, PVT, or Monte-Carlo sign-off.

The result targets single-target feasibility search under a fixed circuit topology: the goal is to find any design satisfying all specifications rather than to optimize a separate figure of merit, and optimization terminates upon finding a feasible design. Experiments cover four benchmark circuits (TSA, CMA, Comp, LDO) using the GF180MCU and SKY130 open-source PDKs, with parameter ranges spanning two orders of magnitude, 10 random specification targets per circuit, and a 500-evaluation SPICE budget. The authors note that simulation time is open-source ngspice runtime rather than extracted-layout, PVT, or Monte-Carlo sign-off, so the overhead fraction would be relatively smaller with slower industrial SPICE. They further suggest the Mapper map is more general than the framework around it, potentially serving as a restart or initialization prior for evolutionary and local search or as a state feature for RL, and plan future work incorporating process-corner topology for PVT-aware sizing.

Several open questions remain for a careful reader: experiments are limited to fixed topologies and single-target feasibility, without layout parasitics, PVT corners, or Monte-Carlo sign-off; the authors explicitly state that using the Mapper map as a restart prior for evolutionary search or as an RL state feature remains untested, and that process-corner topology is future work. In addition, some table values and formula symbols are missing after parsing of the loaded text (for example, the specific FSD numbers per method and the symbols in the acquisition and scheduling equations), so those exact numbers cannot be restated here; readers needing precise convergence iteration counts and hyperparameter values should consult the original tables and equations. Case-study conclusions such as the peak of over 200 regions come from figure-based analysis of the single CMA circuit, and how far they generalize to other circuits and processes still needs more evidence.