Gaussian sampling moves into Ising hardware: Falcon signing core cuts dynamic power about fourfold while diffusion images hold up
Synopsis
Gaussian sampling no longer has to be computed by digital arithmetic: a probabilistic Ising machine produces it from physical stochasticity, and at matched sampling precision the FPGA sampler core uses about 4.0-fold less dynamic power and 4.4-fold fewer logic slices than the isolated Falcon Gaussian core, with diffusion image quality preserved.
Interpretation
Gaussian sampling shifts from arithmetic synthesis in digital logic to a physical process inside probabilistic hardware, with variance and sampling density set by two independent parameters. Falcon-class signatures and diffusion inference previously synthesized discrete Gaussian samples through arithmetic transformations, pseudorandom number generation and rejection sampling in fully digital logic. At matched sampling precision with N+M=32, the FPGA sampler draws about 80 mW of dynamic power, against about 316 mW for the isolated Falcon Gaussian core and about 641 mW for the complete Z-sampler, roughly fourfold and eightfold reductions.
The sampler decomposes Gaussian generation into multiply-and-accumulate, nonlinear activation and probabilistic update, three hardware primitives that can be optimized independently. Digital implementations compute tanh with a lookup table and supply randomness with an Xoshiro128++ pseudorandom number generator, both of which add memory traffic and logic overhead. The all-digital FPGA version uses 450 logic slices and 72 kb of BlockRAM at 32-bit integer precision, while the FPGA/MTJ version uses 323 logic slices and 18 kb of BlockRAM at 27-bit precision, and neither uses DSP blocks.
Replacing the noise source inside an open-source diffusion pipeline leaves generated-image metrics comparable to the software sampler baseline. Edge diffusion inference previously relied on software Gaussian samplers, and repeated noise injection across denoising steps made deployment costly. On Open-Sora with the fixed prompt “Trevi Fountain”, 99 images per sampler were generated and the N=3, M=0 configuration fell within the variability of the software baseline; the Flickr evaluation randomly selected about 500 prompts and generated 10 images per prompt.
Perspective
The report covers the sampling stage itself: two Gaussian samplers, one on FPGA and one combining FPGA with magnetic tunnel junctions, and their comparison inside Falcon-class signing and Open-Sora diffusion decoding. The comparison targets the isolated Falcon Gaussian core and the complete Z-sampler, and does not constitute a full signature-generation accelerator. The roughly 8 mW figure for 28 nm CMOS is a projection obtained by scaling FPGA measurements with the reported FPGA-to-ASIC power ratio, not a fabricated measurement. It is aimed at readers working on post-quantum cryptographic hardware and edge generative inference.
The MTJ implementation matches the target distribution in the high-probability region but shows a small deviation in the extreme tails, which the authors attribute to device-to-device differences and expect to reduce through calibration and tighter control of operating conditions. The MTJ core itself draws about 0.02 mW, roughly two orders of magnitude below the digital pseudorandom-number-generation block, yet system-level energy remains dominated by peripheral circuitry and external multiply-and-accumulate operations, with DAC and ADC stages at about 10 mW per MTJ. The power values come from Vivado power analysis without application-specific activity files, so they represent a conservative near worst-case upper bound.