RTL optimization moves beyond hand rewriting: Dr. RTL cuts timing violations by 21.3% on average across 20 real designs
Synopsis
Optimizing register-transfer-level (RTL) code has long relied on manual rewriting, and existing evaluations mostly measure gains on manually degraded designs under weak synthesis flows, so they cannot show whether a rewrite beats a commercial synthesis tool. Dr. RTL closes a loop of timing analysis, parallel rewriting, commercial synthesis and sequential equivalence checking, and distills successful and failed rewrites into reusable pattern-strategy skills. On 20 original human-written RTL designs it improves worst negative slack (WNS) by 21.3% and total negative slack (TNS) by 16.9% on average over commercial synthesis, with a 5.8% area reduction and an average sequential equivalence check pass rate of 86%.
Interpretation
RTL optimization is placed inside a loop judged by commercial synthesis: an agent rewrites code, and the gain counts only after commercial synthesis and sequential equivalence checking. Earlier RTL optimization evaluations often started from manually degraded designs and used open-source synthesis flows, so gains could reflect recovery of injected inefficiencies or transformations already absorbed by strong synthesis tools. On 36 reference-based tasks, 35 of the 36 human-optimized references still outperform their suboptimal counterparts after commercial compile_ultra synthesis, showing that optimization room remains after synthesis.
Dr. RTL coordinates three specialized agents: one reads post-synthesis timing reports and maps critical paths back to RTL structures, one generates several candidate rewrites in parallel, and one runs commercial synthesis and sequential equivalence checking to return area, timing and correctness feedback. An orchestrator records each optimization trajectory and selects the best equivalent candidate for the next round, tying optimization decisions directly to measured implementation quality. Evaluation uses 20 human-written Verilog designs from open-source projects, averaging 812 lines of code and covering processors, communication interfaces, buffers and signal-processing modules, with 10 iterations and five parallel candidates per iteration per design.
Each attempt is recorded as a diagnosed bottleneck, an applied rewrite, and synthesis plus equivalence-check outcomes; candidates from the same parent RTL are compared by relative result and distilled into pattern-strategy pairs stored in a confidence-aware skill library. Patterns describe recurring bottlenecks such as deep decode logic, high fanout and mux-heavy selection, while strategies describe corresponding transformations such as condition pre-computation, signal replication and arithmetic restructuring; ineffective transformations are also recorded to avoid repeated exploration. In four-fold cross-validation, skills learned from 15 designs were applied to five unseen designs per fold, yielding 47 pattern-strategy entries: 12 high-confidence, 16 medium-confidence, six low-confidence and 13 avoid strategies.
Perspective
The demonstrated scope is 20 original human-written Verilog designs averaging 812 lines and about three modules, evaluated with Synopsys Design Compiler, the Nangate 45 nm standard-cell library and Cadence JasperGold sequential equivalence checking, with 10 iterations and five candidates per iteration per design; power is excluded from the optimization objective because reliable power estimation requires workload-dependent switching activity.
The reported figures are averages; nine of the 20 designs achieve simultaneous timing and area improvement, so not every design improves on both. The average sequential equivalence check pass rate is 86%, meaning some candidates still fail equivalence checking. Skill transfer is evaluated only through four-fold cross-validation, and behavior across toolchains or process nodes is not reported.