AMSchem turns AMS netlists into readable schematics: 85.0% validity on a 40-circuit subset versus 32.5% for direct generation
Synopsis
Much analog and mixed-signal design knowledge lives in schematics, while a netlist records devices and connections but not how a person reads them. AMSchem separates a circuit-aware plan of what to draw from executable schematic geometry, and every revision must pass deterministic checks for device preservation, pin-net consistency and geometric legality. On the 40-circuit schematic subset of AMSchem-Bench, AMSchem with gpt-5.5 reaches 85.0% validity against 32.5% for direct generation; used as a visual feedback module in an LLM analog design loop, it resolves all 13 previously failed AnalogCoder cases across five models.
Interpretation
AMSchem lets a large model produce schematics from AMS netlists that people can read and machines can check, not just text netlists that pass electrical checks. Earlier LLM-based analog design tools iterated mainly over textual netlists and numerical metrics, and their circuits lacked the visual schematics engineers rely on for understanding and debugging. On the 40-circuit schematic subset of AMSchem-Bench, AMSchem with gpt-5.5 reaches 85.0% validity while direct SchematicIR generation reaches 32.5%; by difficulty tier, AMSchem scores 92.3%, 95.0% and 42.9% on Easy, Medium and Hard.
Generation is split into a coordinate-free drawing intent and an executable schematic geometry, with deterministic validators in between. Direct generation entangles connectivity, geometry and drawing syntax in one output, so a local error in symbol placement or routing can silently corrupt the topology, and visual plausibility does not guarantee correct connections. The drawing-intent stage matches netlist fragments to drawing references for 18 common AMS building blocks such as current mirrors and differential pairs through type-constrained subgraph matching, then grounds the plan into SchematicIR carrying source-netlist identifiers; validators check device preservation, pin-net consistency and geometric legality, and only revalidated local patches are accepted.
Rendered-image feedback targets readability defects that no rule can express and writes them back as bounded geometry patches. Structured validation covers only connection and geometry errors expressible as rules, leaving visually ambiguous junctions, obscured terminals and dense wiring outside its reach. The visual feedback stage proposes circuit-aware risk regions, then gives each crop to a visual model together with the corresponding SchematicIR objects, local netlist context and drawing-intent fields; in the ablation, drawing intent alone leaves validity at 32.5%, adding SchematicIR validation and repair raises it to 80.0%, and visual feedback brings it to 85.0%.
Perspective
The demonstrated scope is the 40-circuit schematic subset drawn from AMSnet 2.0 in AMSchem-Bench, plus the downstream design loop on the AnalogCoder benchmark across five models and 120 evaluations; readability is reported through reference-based metrics and a blinded mean opinion score from 15 engineers.
Readability gains are smaller and more variable than validity gains; few-shot examples can lower validity for some backbones; visual feedback is the most token-intensive stage, with a mean total of 153.3k tokens per case, of which input accounts for 88.3%.