SRAM design stops fixing the bitcell first: OpenYieldV2 optimizes 6T and 10T together, raising hypervolume by up to 17.3%
Synopsis
The open-source SRAM design tool OpenYieldV2 turns bitcell topology from a fixed input into an optimizable variable searched jointly with transistor sizing and threshold-voltage assignment. Previously OpenRAM generated layouts without optimizing, and OpenYield's high-fidelity optimization covered only a fixed 6T cell. OpenYieldV2 compiles 6T and 10T macros under identical high-fidelity conditions, predicts performance with a few-shot TabPFN surrogate, and searches with a coarse-to-refined multi-objective optimizer; in mixed-topology scenarios its hypervolume improves by up to 17.3% over the strongest single-topology baseline.
Interpretation
An SRAM bitcell's topology can now be decided by the optimizer together with transistor sizing, instead of being written into the netlist in advance. Among open-source tools, OpenRAM generated full 6T and 10T layouts but performed no optimization, while OpenYield offered high-fidelity evaluation but restricted optimization to scalar sizing of a fixed 6T cell. Across three design scenarios, joint search improved both hypervolume and IGD over Separate-Union, which splits 1000 evaluations evenly between the two topologies; in scenario S3, whose feasible front is strongly 10T-dominant, joint search still assigned most evaluations to 10T and beat that baseline.
Joint search first spreads evolutionary search over the discrete choices, then refines continuous sizing by gradient within each selected architecture. Discrete topology and threshold-voltage choices are handled by surrogate-guided evolutionary search, while continuous transistor sizes are refined by residual-adaptive gradient descent after the discrete configuration is fixed, so each variable type gets a suited search method. All methods share one TabPFN surrogate conditioned on 500 SPICE samples with 1000 surrogate evaluations per run; in the joint-topology setting the complete optimizer raises hypervolume by 17.3% and lowers IGD by 90.1% relative to fixed-topology SPEA2, and the coarse-search-only variant reaches hypervolume 1.023 against 1.045 for the complete version.
Topology preference is not a fixed design rule but a boundary that moves with supply voltage and noise-margin and delay constraints. The prior practice picked one topology by experience at design time and optimized only sizing; joint search shows 6T and 10T jointly shape the Pareto front under most design conditions, with topology-dominant regions appearing only under stringent requirements. At 0.5 V supply, 10T raises hold noise margin by 23.0%, read noise margin from 0.071 V to 0.110 V, and write noise margin by 9.2% over 6T, at the cost of read delay growing from 0.546 ns to 0.795 ns, so the two topologies trade advantage with conditions.
Perspective
The demonstrated scope is the 6T and 10T bitcell topologies in FreePDK45, with evaluation at nominal and near-threshold supply, at TT and across PVT corners, and candidate circuits validated nominally with Xyce at 32 KB capacity, 16 output columns, and interconnect RC parasitics enabled. The intended readers are circuit and EDA researchers working on SRAM macro design and memory compilers.
The topology preference boundary is characterized here only between 6T and 10T on FreePDK45; whether it holds a similar structure for additional bitcell topologies and advanced technology nodes remains open. The surrogate's labeled context is established before the search and stays fixed throughout each run, queries add no new SPICE-labeled samples, and uncertainty-based acquisition is not used.