CUDA 13.5 moves Vera Rubin from developer preview to production, and Windows on Arm reaches DGX Station
Synopsis
NVIDIA released CUDA 13.5, moving support for the Vera Rubin platform from early developer access to general availability for enterprise production; Windows on Arm support, GA since CUDA 13.4, now extends to DGX Station for Windows. The same release adds GPU scheduling customization through locality domains and MPS v3, a preview of multi-GPU communication and SIMT library calls inside CUDA Tile kernels, and updates across CUDA Python, CCCL and the math libraries. These capabilities target developers deploying to known architectures, and the benefit depends on the chosen platform and configuration.
Interpretation
CUDA 13.5 moves Vera Rubin from early developer access to general availability, ready for enterprise production, and extends Windows on Arm support from its CUDA 13.4 GA state to DGX Station for Windows. Previously Vera Rubin was available only through early developer access, and Windows on Arm GA did not yet cover DGX Station for Windows. NVIDIA states this status change in the CUDA 13.5 release material; it is a change in supported platform scope, not a performance measurement.
For scheduling, applications can choose uniform streaming multiprocessor partitions across locality domains or partitions that include all available SMs. By default, localized green-context partitions use the same guaranteed SM count per domain, leaving supplemental SMs outside those partitions. The new cudaDevSmResourceGroupLocalityDomainSupplementalSms flag, combined with cudaDevSmResourceGroupLocalityDomainId, includes those extra SMs in each selected domain, at the cost that partitions may differ in size; discovery mode in cudaDevSmResourceSplit() reports each partition's SM count so work can be distributed accordingly.
MPS v3 gives finer control over how workloads share a GPU, from scheduling individual servers to assigning resources to groups of clients, including weighted timeslicing, SM partition load balancing, cgroup-based routing and per-namespace SM partition assignments. Earlier MPS releases did not offer the same granularity of control over these scheduling dimensions. Weighted timeslicing sets a base timeslice per MPS server and tunes switching independently; load balancing borrows with --max-chunks and lends with --shareable=true, and MPS reclaims borrowed resources before reassigning them while applications keep a stable base partition size.
CUDA Tile kernels can now perform multi-GPU communication inside the kernel and, in preview, call device functions from SIMT libraries. Before this release, Tile and SIMT library code could only be combined across kernel boundaries, with data passing through global memory. Unicast pointers access memory on another NVLink-connected GPU, while multicast pointers and dedicated multimem operations support reductions and stores across GPUs on NVSwitch fabrics with NVLink SHARP; the preview covers library functions only, and calling custom __device__ functions from tile code is planned for a future release.
Perspective
The report covers the CUDA 13.5 features and support status NVIDIA published, for researchers and engineers who develop or deploy on CUDA; performance figures apply only to the library, algorithm and GPU conditions they are labeled with.
Tile-SIMT interop is a preview in 13.5 and covers library functions only, with calling custom __device__ functions planned for a future release; some library performance figures are given as geometric means or ranges and are tied to specific GPUs and algorithm versions.